Log

Setting up the day Two weeks earlier I’d hit a wall: the AD9361’s state machine could reach ALERT but nothing I did would push it further, because reaching real RX state needed a second PLL — the RX local oscillator synthesizer — that I hadn’t touched at all. This post is about the day that wall came down. It ended up being the longest single day of the project so far, and it’s the one I’d point to first if someone asked what this project has actually been like to work on. ...

Wiring up the RX digital interface With the hang from the last post resolved, I finally had a stable enough platform to start on the part of this project I actually care most about: getting real samples out of the AD9361. First step was wiring ad9361_if_rx.sv — the RX-only LVDS digital interface — into the top level, which meant I needed the chip’s digital and ADC sample-rate logic actually clocked before any of it would do anything useful. ...

The symptom With SPI alive and the AXI address map sorted out, the console would run fine for a while and then just stop. Completely unresponsive — sometimes while idle, sometimes under active traffic — and the only fix was a full software reload. No bitstream reload needed, no power cycle. Whatever was going wrong lived in software state, not in the PL. That’s a genuinely unpleasant kind of bug to chase, because “sometimes, after a while, for no obvious trigger” rules out almost every fast debugging technique you’d normally reach for. What follows is the order I ruled things out, because the order matters as much as the answer. ...

Closing a loop The single-cycle RISCV32I post ended with a promise: “this single-cycle design became the baseline for the pipelined RISCV32I CPU I’m currently building… that comparison is next up.” That comparison took longer than expected to actually write up — not because the work stalled, but because the pipeline got finished, timing got closed, and I moved on before circling back to put it into words. This is that write-up, reconstructed from the actual RTL and the real Vivado timing reports rather than from memory, because at this point the project genuinely isn’t fresh anymore. I’d rather tell it accurately from the evidence than paraphrase what I think I remember. ...

A new project: building a Pluto clone from scratch After the RISC-V detour, I’m back on the RF side of things, which is really where this whole hobby started for me. The new project is fm_receiver: a Zynq-7020 SDR receiver built around a HamGeek board carrying an AD9361 — the same RF transceiver chip at the heart of Analog Devices’ own ADALM-Pluto. Custom AXI peripherals, bare-metal Cortex-A9 firmware with no FSBL, no BSP, no OS, and an AD9361 bring-up sequence I’m deriving register-by-register against ADI’s own reference driver rather than copying an example project. Pure non-project batch-mode Vivado throughout — I’ve never once created a .xpr file for this. I’ll be documenting it here the same way I documented the CPU build: as it actually happens, wrong turns included. ...

The Question I Didn’t Know I Had I never fared well with the school system. Not because I lacked curiosity — if anything, I had too much of it. I always wanted the deep version of things, not the pass-the-exam version. The problem was I had no way to get there. The traditional path for that kind of depth is a PhD: years under a mentor who steers you, who knows which question to ask before you even know you need to ask it. I didn’t take that path. Instead, for years, my way of chasing knowledge was the same as most people’s — open a browser, search, read, repeat. ...

Introduction Perhaps it’s only me, but I believe anyone who is serious at digital design should at least try to implement a simple processor. This is the first of a series aimed to end with a usable processor for my projects, in an attempt to learn some of the concepts of computer architecture, while at the same time honing my hardware design skill. This post is a technical overview of the design choices behind it: where I made reasonable calls, where I got it wrong, and what I learned along the way. ...

Why I Started Learning Digital Design I was ten years old when I first touched a computer. I don’t remember much of that first encounter, except one thing: I became obsessed with the idea of the Arithmetic and Logic Unit. My teacher mentioned it once, briefly, the way you mention something to a room full of ten-year-olds — no details, just the name. But in my head, the ALU became this almost mythical machine. Something that could take any calculation, any problem, and just… solve it. I didn’t know how. I just knew I wanted to. ...

Introduction Let me take a detour from the HDL and digital things and go back for a while into the analog domain. For this whole system I’m building to be of any use, the signal from the guitar has to have enough amplitude to: Dominate the noise of the processing chain Use as much of the XADC’s dynamic range as possible In any case, I need something simple, while also thinking I wouldn’t be able to respect myself if I built it as a circuit mounted on a breadboard. So, I also took the chance to learn PCB production in a long afternoon. ...

Introduction On this little project of making a guitar effect chain, the equalizer/filter will be a central component. The guitar has a particular spectrum, and not everything within the 20KHz humans can hear needs to be processed. In filtering out the unnecessary frequencies we get some benefits: All the spectral content is useful information, increasing the amount of signal we can process We are cutting noise, which is usually very wideband, often modeled as uniformly distributed All of this translates into a better signal-to-noise ratio (SNR). ...