Hdl

Setting up the day Two weeks earlier I’d hit a wall: the AD9361’s state machine could reach ALERT but nothing I did would push it further, because reaching real RX state needed a second PLL — the RX local oscillator synthesizer — that I hadn’t touched at all. This post is about the day that wall came down. It ended up being the longest single day of the project so far, and it’s the one I’d point to first if someone asked what this project has actually been like to work on. ...

Wiring up the RX digital interface With the hang from the last post resolved, I finally had a stable enough platform to start on the part of this project I actually care most about: getting real samples out of the AD9361. First step was wiring ad9361_if_rx.sv — the RX-only LVDS digital interface — into the top level, which meant I needed the chip’s digital and ADC sample-rate logic actually clocked before any of it would do anything useful. ...

The symptom With SPI alive and the AXI address map sorted out, the console would run fine for a while and then just stop. Completely unresponsive — sometimes while idle, sometimes under active traffic — and the only fix was a full software reload. No bitstream reload needed, no power cycle. Whatever was going wrong lived in software state, not in the PL. That’s a genuinely unpleasant kind of bug to chase, because “sometimes, after a while, for no obvious trigger” rules out almost every fast debugging technique you’d normally reach for. What follows is the order I ruled things out, because the order matters as much as the answer. ...

Closing a loop The single-cycle RISCV32I post ended with a promise: “this single-cycle design became the baseline for the pipelined RISCV32I CPU I’m currently building… that comparison is next up.” That comparison took longer than expected to actually write up — not because the work stalled, but because the pipeline got finished, timing got closed, and I moved on before circling back to put it into words. This is that write-up, reconstructed from the actual RTL and the real Vivado timing reports rather than from memory, because at this point the project genuinely isn’t fresh anymore. I’d rather tell it accurately from the evidence than paraphrase what I think I remember. ...

A new project: building a Pluto clone from scratch After the RISC-V detour, I’m back on the RF side of things, which is really where this whole hobby started for me. The new project is fm_receiver: a Zynq-7020 SDR receiver built around a HamGeek board carrying an AD9361 — the same RF transceiver chip at the heart of Analog Devices’ own ADALM-Pluto. Custom AXI peripherals, bare-metal Cortex-A9 firmware with no FSBL, no BSP, no OS, and an AD9361 bring-up sequence I’m deriving register-by-register against ADI’s own reference driver rather than copying an example project. Pure non-project batch-mode Vivado throughout — I’ve never once created a .xpr file for this. I’ll be documenting it here the same way I documented the CPU build: as it actually happens, wrong turns included. ...

Introduction Perhaps it’s only me, but I believe anyone who is serious at digital design should at least try to implement a simple processor. This is the first of a series aimed to end with a usable processor for my projects, in an attempt to learn some of the concepts of computer architecture, while at the same time honing my hardware design skill. This post is a technical overview of the design choices behind it: where I made reasonable calls, where I got it wrong, and what I learned along the way. ...

Introduction On this little project of making a guitar effect chain, the equalizer/filter will be a central component. The guitar has a particular spectrum, and not everything within the 20KHz humans can hear needs to be processed. In filtering out the unnecessary frequencies we get some benefits: All the spectral content is useful information, increasing the amount of signal we can process We are cutting noise, which is usually very wideband, often modeled as uniformly distributed All of this translates into a better signal-to-noise ratio (SNR). ...

Introduction It took me a while to come up with worthy content, but here I am. I have been working on getting my FPGA board to sample analog audio with the internal ADC for a project proposed by a colleague as a way to learn the intricacies of digital design. Let me tell you straight: the documentation for the ADC on this Artix 7 device does a great job of being confusing. I’m not ashamed to say that this is the part that took me the longest to figure out, also considering my paranoia about damaging the components with non-compliant voltages. ...

Introduction Last time, we built a circuit together using Verilog to communicate with an I2S device. But we never delved into how to make a waveform for it. Now, don’t get me wrong: if you did the blinky LED example when starting your first projects, this should be easy for you: A square pattern is just zeros and ones A saw pattern is a counter from zero to max A triangle wave is a counter that goes back after hitting max or min values A sine wave is just some CORDIC… Now, we will not be using CORDIC and will not be doing simple counters. I want to show you a couple of tricks to generate a clean sine waveform that you can later compose to create fancier sounds. ...

Introduction While keeping sight of my target when doing this project, there were some components on the Arty that I don’t really know how to use. One of these was the DRAM mounted on the board. Hence, I wanted to implement the most obvious effect that needs some kind of memory of previous samples. Basically, at some point in the chain, the delay will take samples at a rate of 48KHz, store them in a circular buffer in RAM, and set up a read pointer at some distance from the write pointer, such that reading yields back audio from the past. The math for this is quite simple in the end: with a sampling rate of 48KHz, every memory address of distance between read and write adds ~20.8 microseconds of delay. So let’s say I want a delay of up to ~2 seconds — we’ll need 192000 bytes of memory. It’s honestly not even that much when the mounted memory is 1GByte. ...