Arch

Closing a loop The single-cycle RISCV32I post ended with a promise: “this single-cycle design became the baseline for the pipelined RISCV32I CPU I’m currently building… that comparison is next up.” That comparison took longer than expected to actually write up — not because the work stalled, but because the pipeline got finished, timing got closed, and I moved on before circling back to put it into words. This is that write-up, reconstructed from the actual RTL and the real Vivado timing reports rather than from memory, because at this point the project genuinely isn’t fresh anymore. I’d rather tell it accurately from the evidence than paraphrase what I think I remember. ...

Introduction Perhaps it’s only me, but I believe anyone who is serious at digital design should at least try to implement a simple processor. This is the first of a series aimed to end with a usable processor for my projects, in an attempt to learn some of the concepts of computer architecture, while at the same time honing my hardware design skill. This post is a technical overview of the design choices behind it: where I made reasonable calls, where I got it wrong, and what I learned along the way. ...