Who am I?
Valeggio, 2023
I’m Daniel, a microelectronics engineer working on cutting edge optical links, but with a general passion for electronics since I was 13 years old. Based in Italy, from the best analog microelectronics school around (and they know it).
What is this blog about
In principle, I wanted to make a web log for my learning activity on digital design and FPGA. But well in the deep, I’m an analog circuit designer, and even deeper, a physicist. So I guess at some point the arguments will diverge onto many of my interests. But what blog writer doesn’t do that?
Why is this blog necessary?
I used to write blogs back in the 2010s about machine learning, data science and numerical simulation of complex systems. With the years I moved onto different things and removed the blog references. But in the end I like the learning process that allows the writing and summarizing information. If other people can understand it, that means I got it right. Akin to the teacher learning from the student, just that the student is me as well.
So basically, it is necessary for me, but with the hope that the quality is high enough so that you can leverage on this information as well.
Why there is that little shack in the navbar?
Among many of my dreams, there is this dream of going off the grid (partially). So I’m looking for ways to have this small house in the mountains, some mini cows, mini donkeys, goats, chickens and Wi-Fi to keep doing what I love. This blog itself is a move towards that future, hence I see the point on putting a symbol of my end goal somewhere around where I don’t lose sight of it.
Publications
1 A 200Gb/s Low Power DSP-Based Optical Receiver and Transmitter with Integrated TIA and Laser Drivers
2 A 5nm 60GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 34dB SNDR up to 32GHz
3 A 5-nm 60-GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 35.2dB SNDR up to 32 GHz
4 An Eight-Lane 800-Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5-nm FinFET Process